BlueLynx Chiplet Interconnect

Simplify chiplet complexity with a customizable die-to-die IP solution

Ease the Architecture and Design Process

Chip makers need solutions tailored to their specific applications and workloads. At the same time, they want to reap the advantages of working within the context of industry standards. Our solutions deliver on both, offering standards-based customizability that supports high bandwidth requirements.

Blue Cheetah’s BlueLynx™ die-to-die (D2D) adaptive interconnect subsystem IP provides physical (PHY) and link layer chiplet interfaces supporting Universal Chiplet Interconnect Express (UCIe) and Open Compute Project (OCP) Bunch of Wires (BoW).

 Streamline the Transition from SoCs to Chiplets

BlueLynx efficiently connects to on-die buses and network-on-chip (NoCs) with various standards, including AMBA® 4 CHI, AXI, ACE, and more. Integrating BlueLynx PHY IP solutions with NoC subsystems enables system architects to create innovative new designs faster and cheaper.

Customers receive an industry-standard ASIC integration view with a reference platform and software for rapid silicon bring-up, ensuring first-pass silicon success. Die-to-die subsystem solutions are PPA-optimized and offer advanced and low-cost packaging options.

Silicon-proven BlueLynx D2D IP is available in over seven nodes—including 16nm,12nm, 7nm, 6nm, 5nm, 4nm, 3nm and below—and across multiple semiconductor foundries, providing a cost-effective solution for your application needs.

 Advanced Customizable Architecture

Blue Cheetah’s revolutionary architecture delivers industry-leading silicon utilization for high-bandwidth links. BlueLynx offers the optimal chiplet interconnect IP with the best bandwidth, energy efficiency, low latency, maximum link reach, bit error rate, and packaging and process options.

Customizable

BlueLynx PHY and link layer architecture is customizable to support a wide range of physical and complex system bandwidth use cases.

Configurable

Whether your application is cost-sensitive or performance-intensive, BlueLynx offers versatile packaging options, including standard and advanced, with support for multiple bump pitches, metal stacks, and poly orientations.

Optimized

BlueLynx D2D IP solutions offer power-optimized performance from 8 Gb/s to 16, 24, 32, and beyond.

Multiple Processes

BlueLynx IP is available at 16nm,12nm, 7nm, 6nm, 5nm, 4nm, 3nm, and below across multiple semiconductor foundries and supports various medal stacks.

Silicon Proven

Customers receive industry-standard ASIC integration views with reference collateral, including board package designs and a bring-up platform and software required for first-pass silicon success in the shortest time.

 Use Cases

Dual Mode PHY Custom IP

BlueLynx PHY IP is one side of a die-to-die parallel interface delivered as a single GDS Hard IP and a single RTL Soft IP. The PHY is compatible with UCIe and BoW specifications. It is intended to interface with a second interface that complies with the same requirements. Multiple PHY slices can be stacked for higher bandwidth per millimeter of silicon die edge. UCIe compatible D2D solutions support UCIe v1.1 FLIT Data Interface (FDI). BlueLynx enables customers to configure the bump pitch to accommodate advanced packaging. The bump pitch will determine the overall PHY hard macro area.

  • High data rate of 2–24 Gb/s
  • Very low power of < 0.375 pJ/bit @ 2–16 Gb/s 0.5-V VDDQ
  • Very low latency of < 2 ns PHY-to-PHY
  • Support for 2:1, 4:1, 8:1, 12:1 and 16:1 serialization and deserialization ratios
  • Support for bonded and independent slices
  • Side band and redundancy support
  • Staggered bump pitch for organic substrate (example macro above)
  • Bump pitch customizable from 45um (advanced) to 180um (standard) package applications
  • Each slice (TX+RX) macro area set by macro bump pitch (multiple slices can be stacked)
  • Support for N/S and E/W Poly Orientations
  • Programmable alignment between link layer and PHY clocks to aid timing closure
  • APB pclk pass-through to the link layer clock domain for reset of synchronous flops
  • Integrated, background-calibrated DLL with duty-cycle correction for input clock
  • Firmware-controlled startup and shutdown through control and status registers
  • JTAG and/or APB register access
  • Built in self-test (BIST) and diagnostic logic
  • On Demand eye plotter
  • Integrated microcontroller, PLL

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